The global advanced chip industry is entering a new stage of competition. In the past, competition in the field of chip manufacturing often focused on the advancement speed of process nodes, evolving from 7 nanometers, 5 nanometers to 3 nanometers, and then to 2 nanometers and more advanced nodes. But as advanced process technologies continue to approach physical limits, the factors that determine chip competitiveness are becoming more complex.

At present, TSMC, Samsung, and Intel are still the three most closely watched participants in the field of advanced logic chip manufacturing. At the same time, chip design companies such as NVIDIA and AMD, as well as high bandwidth memory manufacturers such as SK Hynix and Micron, and key equipment suppliers such as ASML, together form the advanced chip industry chain.

This means that the next stage of chip competition is no longer just about“ Who will achieve smaller processes first; It is a comprehensive competition between manufacturing processes, transistor structures, lithography equipment, advanced packaging, high bandwidth memory, and AI computing requirements.

TSMC continues to advance 2-nanometer and more advanced processes

TSMC is still in an important position in the field of advanced logic processes.

The 2-nanometer process adopts a fully enclosed gate (GAA) transistor architecture, which provides a new technological path for further improving performance and reducing power consumption by changing the control method of the transistor gate on the channel compared to the previous FinFET structure. According to the established plan, TSMC's 2-nanometer process will enter mass production in the fourth quarter of 2025, while A16 technology is planned to enter mass production in the second half of 2026.

2 nanometers does not necessarily mean that there is a structure with an actual size of 2 nanometers inside the chip. Modern process nodes are more of a technological generational name used to represent the comprehensive improvement of a series of indicators such as transistor density, performance, power consumption, and manufacturing capability.

Therefore, after entering the era of 2 nanometers, the importance of process names themselves is decreasing, while the importance of actual transistor density, unit power performance, yield, and large-scale production capability is further increasing.

For AI processors, high-performance computing chips, and high-end mobile processors, these indicators directly affect the computing power, energy consumption, and deployment costs of the final product.

The three advanced process routes are gradually diverging

Another change in the competition of advanced manufacturing is that different manufacturers are beginning to form technology routes with their own characteristics.

Samsung OEM regards 2 nanometers as an important node to catch up with advanced processes. Its new generation process also uses fully surround gate transistors, and plans to further expand related technologies from mobile processors to high-performance computing and automotive chip applications.

Full surround gate is not a simple transistor structure upgrade. As the size of transistors continues to shrink, the control capability of traditional FinFET channels is gradually facing challenges. GAA can further enhance gate control capability by surrounding the channel from multiple directions, thereby improving leakage and energy efficiency performance.

Intel has chosen another technological path. Its 18A process combines technologies such as RibbonFET full surround gate transistor and PowerVia backside power supply, hoping to improve the performance and energy efficiency of advanced nodes through synchronous adjustment of transistor structure and power supply mode.

18A is expected to enter mass production in 2025. At the same time, high numerical aperture EUV lithography technology has been used in some 18A related manufacturing processes, becoming an important node in the evolution of advanced manufacturing technology.

From this perspective, the competition among TSMC, Samsung, and Intel is no longer simply about catching up on nodes, but rather a comprehensive competition centered around transistor architecture, power supply methods, lithography capabilities, manufacturing yield, and customer ecology.

From“ Nano Competition; Shift towards actual computing performance

For chip design companies, advanced manufacturing processes are only a basic condition for achieving high-performance chips.

NVIDIA and AMD are not wafer foundry companies themselves, but typical chip design companies. Two companies are responsible for key aspects such as processor architecture, chip design, and platform ecology, which are then completed by advanced manufacturing partners for wafer production.

NVIDIA currently has a strong market influence in the AIGPU field, and its data center processors need to meet requirements such as computing density, memory bandwidth, interconnect capability, and energy efficiency simultaneously. AMD covers multiple computing fields such as CPUs, GPUs, and AI accelerators, and continues to advance its product layout for data centers and AI applications.

This also explains why advanced processes alone cannot determine the final performance of an AI chip.

Even if an advanced AI processor adopts the latest manufacturing nodes, its overall computing power may still be limited if the memory bandwidth is insufficient, the interconnection efficiency between chips is low, or the packaging cannot support sufficiently high power density.

Therefore, advanced chips are shifting their competition from single chips to; Computing chip+memory+packaging+interconnection; System level competition.

HBM becomes an important component of AI chips

As the scale of AI models expands, processors need to continuously read large amounts of data from memory. Traditional memory architectures are gradually unable to meet the bandwidth requirements of some high-performance AI computing tasks, making high bandwidth memory (HBM) an important component of AI infrastructure.

Memory manufacturers such as SK Hynix and Micron are playing an important role in this field.

HBM stacks multiple layers of DRAM and utilizes advanced packaging and high bandwidth interfaces to enable processors to obtain large amounts of data in a shorter amount of time. For training and inference tasks, the number of computing units is certainly important, but if data cannot be delivered to the processor in a timely manner, computing resources cannot be fully utilized.

Therefore, the competition for future AI chips cannot only rely on GPUs or AI accelerators themselves, but also needs to observe HBM capacity, bandwidth, power consumption, and packaging integration capabilities.

From the perspective of the industrial chain, this also means that advanced logic processes are forming a closer connection with advanced storage manufacturing.

ASML masters the important technical aspects of advanced lithography

If wafer manufacturing companies decide how chips are produced, then lithography equipment determines whether many advanced structures can be manufactured.

ASML is one of the core enterprises in the advanced lithography equipment industry chain. EUV lithography technology has become an important manufacturing tool for advanced logic processes, and as the process shrinks further, the resolution and process complexity issues faced by traditional EUV become more prominent.

High numerical aperture EUV, also known as High NAEUV, further enhances exposure resolution by increasing the numerical aperture of the optical system, and is considered an important technological direction to support future advanced nodes.

High NAEUV is not simply about improving equipment accuracy. It also involves multiple stages such as masking, photoresist, process control, computational lithography, and wafer manufacturing processes. Therefore, the evolution of advanced lithography equipment will actually affect the entire chip manufacturing system.

With the gradual advancement of the 2 nanometer and subsequent nodes, the degree of collaboration between lithography equipment, wafer fab processes, and material supply chains will be further improved.

Advanced packaging is becoming a new competitive focus

In the past, the improvement of chip performance mainly relied on an increase in the number of transistors and a reduction in the manufacturing process. But after advanced nodes, it becomes increasingly difficult to achieve performance improvement solely by reducing transistor size.

Advanced packaging has therefore become a new technological growth point.

Through technologies such as 2.5D, 3D packaging, and Chiplets, chips or chips with different functions can be combined into one packaging system. AI accelerators can be integrated with HBM at high density, and different computing chips can be manufactured using different manufacturing processes based on their functions.

This approach can reduce the impact on; All functions must use the same advanced process; The dependence.

For example, the computing core can adopt advanced nodes, while I/O, analog circuits, or other auxiliary modules use relatively mature manufacturing processes and are integrated through advanced packaging. This not only helps to control manufacturing costs, but also improves the flexibility of chip design.

For AI processors, this change is particularly evident. As the size, power consumption, and manufacturing cost of individual chips continue to rise, the importance of system level integration is rapidly increasing.

AI demand is redefining advanced chips

The demand for AI computing is an important factor driving the continuous evolution of advanced chip technology.

Traditional CPUs focus more on general computing power, while AI processors need to simultaneously solve problems such as matrix computing, memory access, data transmission, and parallel computing. As the model size grows, communication and memory access between processors have become important factors affecting overall performance.

This has led to a clear trend in the advanced chip industry:

Advanced processes are responsible for increasing computational density, HBM is responsible for providing data, advanced packaging is responsible for connecting computing and memory, and high-speed interconnection is responsible for expanding the scale of the entire computing system.

Therefore, the improvement of chip performance in the future may increasingly rely on the joint progress of multiple technological links, rather than the upgrade of a single process node.

Advanced chip competition enters; System Engineering; Stage

From the advanced processes of TSMC, Samsung, and Intel, to the processor designs of NVIDIA and AMD, to SK Hynix and Micron's HBM, and ASML's advanced lithography equipment, the global advanced chip industry has formed a highly complex technology collaboration system.

Any progress in any of these aspects may affect the performance and commercialization capability of the final chip.

The competition for advanced chips in the future will continue to revolve around at least several directions: more advanced transistor architectures, more efficient power supply methods, higher resolution lithography, more mature advanced packaging, higher bandwidth memory, and more efficient inter chip interconnects.

This also means that; 2 nanometers; “ 1.4 nanometers; Although waiting for process nodes still holds significant importance, it is no longer sufficient to summarize the technological level of the chip industry.

What truly determines the competitiveness of the next generation of computing platforms will be the complete system capabilities from transistors to packaging, from memory to interconnects, from wafer manufacturing to software ecosystems. As the demand for AI, high-performance computing, and data centers continues to grow, the competition in the advanced chip industry will gradually shift from a competition of single manufacturing nodes to a competition of overall computing system efficiency.